In recent years, devices to operate in a high frequency range such as a millimeter wave band, a submillimeter wave band, and a THz band have been proposed. An automotive radar that utilizes the millimeter wave band, an equipment for a fifth generation mobile communication system, an imaging device that utilizes the THz band, and so forth are proposed, for example.
On the other hand, as a semiconductor device manufactured by a complementary metal-oxide semiconductor (CMOS) process of the related art, there is a semiconductor device in which transistors are arranged in a gate length direction and in which gate electrodes are arranged by using a multi-finger structure. Note that, in a gate, a drain, or a source of a transistor manufactured by the CMOS process, parasitic resistance or parasitic capacitance is produced. Gate resistance, drain capacitance, and drain resistance, which are included in the parasitic resistance or the parasitic capacitance, are reduced, thereby increasing a maximum operating frequency of the transistor. The gate resistance and the drain capacitance depend on a wiring electrode pattern connected to the transistor.
However, in a semiconductor device of the related art, which has the multi-finger structure, there is a problem that, in the stand points of reliability and a layout, it is difficult to fully reduce the gate resistance or the drain capacitance and it is difficult to increase the maximum operating frequency of the transistor.
The followings are reference documents.
[Document 1] International Publication Pamphlet No. WO 2007/072844,
[Document 2] Japanese Laid-open Patent Publication No. 2007-158139, and
[Document 3] Japanese National Publication of International Patent Application No. 09-505689.